Are TLBs in same power domain as ARM core logic ?

Applies to: ARM1176

Scenario

When I put my chip into deep sleep mode, it puts the ARM core into power down.

In this case what is the state for the micro TLBs and main TLB? Are they in
power down also? Do I need to initialize them after wakeup?

Answer

ARM1176 supports 4 power management mode:

            - run (everything clocked and power)

            - standby (power on but most of the clocks gated)

            - shutdown (power off)

            - and optionally dormant mode (power off to the logic but retained on the RAMs)

So which TLB state will be lost depends on which parts of the processor are powered down. Lockdown
entries would need to be restored, as they are made from flip-flops in the core.
The micro TLB is also made from flip-flops rather than compiled RAM so its state will be lost when
the power is removed.

The main TLB is compiled RAM and its state will be retained if you have implement a dormant mode
where power can be retained to the RAMs. Dormant mode is an implementation option, requiring that the user add a separate power domain for the RAMs.

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