ARM Technical Support Knowledge Articles

How should cache maintenance operations be handled in systems with multi-level cache, with reference to DMA?

Applies to: Cortex-A9, Processor Cores


In systems with multiple layers of caches, some care is needed when performing cache maintenance activity where the implementation does not provide atomic cache maintenance operations. This means systems where cache maintenance must be performed separately on L1 and L2 caches. Examples of such systems include Cortex-A9 coupled with L2C-310, or Cortex-A5 coupled with L2C-310. A particular area of concern is where there are multiple CPUs sharing L2 cache and there is a possibility that one CPU may access memory while another CPU is performing cache maintenance operations. ARM processors provide three kinds of cache maintenance operation, with provision for such operations to be broadcast between processors in an MPCore system. Such operations may be required when an external DMA is available in the system and is not participating in automatic cache coherency management.

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