ARM Technical Support Knowledge Articles

What AXI ID mapping does the PL310 r3p1 use ?

Applies to: AXI PL310 L2CC


Reference to AXI ID mapping has been removed from r3p1 TRM, so that customers do not rely on these values. It is possible for the mapping to change between IP revisions (as was the case from r2p0 to r3p0).

Customers can refer to the r3p0 document, which contains AXI ID mapping (still valid for r3p1).

One errata to be aware of in the mappings table is:

'Linefill generated by cacheable read miss from slave S0 or S1'

in 'Table 2-5 Master port ID values for reads' of the PL310 r3p0 TRM should read:

'Linefill generated by cacheable read miss or non-cacheable read from slave S0 or S1'

Rate this article

Disagree? Move your mouse over the bar and click

Did you find this article helpful? Yes No

How can we improve this article?

Link to this article
Copyright © 2011 ARM Limited. All rights reserved. External (Open), Non-Confidential