|ARM Technical Support Knowledge Articles|
Applies to: AXI L220 L2CC
We have following queries
1) How is the TAGCLKEN generated for clock ratio 3:1
2) What phase relationship is expected between CLK and TAGCLKEN
3) Please provide the similar timing diagram for READ_LATENCY = 2 and 3 , with clock ratio 3:1.
4) How do we make sure the clock is generated dynamically , with READ_LATENCY,WRITE_LATENCY
AND SETUP_LATENCY being programmable . as registers are not visible outside PL310.
5) Can we use always use TAGCLKOUT as TAGCLK , if our memory supports it?
Find attached visio diagram showing 3:1 clock ratio TAGCLK. As you can see, TAGCLKEN is generated
on the rising edge of CLK.
If you require the RAM clock to equal the CLK frequency, you use fig 2-17 TAGCLKOUT to clock the
RAM, which uses an internal clock gate and does not use TAGCLKEN signal.
If you require RAM clock to be a division of CLK frequency, you use external RAMCLK and an
external clock gate, and connect TAGCLKOUTEN to the clock gate to generate TAGCLK, as shown in
fig 2-17. It may not be appropriate to use TAGCLKOUT as the memory clock in this case because the
pulse is "narrow" (only the width of CLK).
Refer to figure 2-19 for the read latency illustration. The number of cycles of latency is equal
to the number of cycles which TAGRD is delayed after the memory clock rising edge. With zero
latency, RAM clock changes on CLK edge 0 and TAGRD is read on clock edge 1. With 0x1 latency, RAM
clock changes on CLK edge 0 and TAGRD is read on CLK edge 2 (as shown in fig 2-19), etc.
External RAMCLK is not generated dynamically – it is always active and does not depend on latency
Did you find this article helpful? Yes No
How can we improve this article?