ARM Technical Support Knowledge Articles

What is the pupose of ACP signals ARUSERS[4:0], AWUSERS[4:0] on Cortex-A9 MPCore ?

Applies to: Cortex-A9

Answer

AxUSER[0] is ANDed with AxCACHE[1] to decide if it is a coherent shared request. Such requests can access level-1 cache coherent data.

The other bits of AxUSER are simply copied from the ACP slave port to the AMBA master port for
non-coherent requests, which pass through the core unmodified.

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