|ARM Technical Support Knowledge Articles|
Applies to: Cortex-A9
AxUSER is ANDed with AxCACHE to decide if it is a coherent shared request. Such requests can access level-1 cache coherent data.
The other bits of AxUSER are simply copied from the ACP slave port to the AMBA master port for
non-coherent requests, which pass through the core unmodified.
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