ARM Technical Support Knowledge Articles

How does Cortex-A5 make use of data linefill buffers 0 and 1 ?

Applies to: Cortex-A5

Answer

AXI read IDs are marked as:

b010  for linefills and non-cacheable bursts from linefill buffer 0.

b011  for linefills and non-cacheable bursts from linefill buffer 1.

For any given L1 data cache line-fill LFB0 will be used if available. LFB1 will be used if LFB0

is busy (assuming there is no hazard on the request in LFB0). Also only LFB0 is used for data

prefetch.


So if the miss-rate is low with only the occasional AXI transaction only LFB0 will be used, but

if the miss-rate is high you should expect to see alternate LFB0, LFB1 requests on the interface.

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