ARM Technical Support Knowledge Articles

Can you explain byte selection in ARM1176 big-endian BE-32 system ?

Applies to: ARM1176

Answer

Refer to Tables 4-4 and 4-5 in the TRM.

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0333h/Cdfibidj.html

If you use BE-32, both instruction and data endianess become big-endian and unaligned accesses
are not permitted.

1.      Word-sized, word-aligned store

Register r0 = 0x76543210,  r6=0x1000 and we execute  STR  r0, [r6]

In little-endian mode, WDATARW = xxxxxxxx76543210, WSTRB = 0F

If we use BE-8 or BE-32, then WDATARW = xxxxxxxx10325476, WSTRB = 0F

2.      Word-sized, unaligned store

Register r0 = 0x76543210,  r6=0x1000 and we execute  STR  r0, [r6, #1]

In little-endian mode, this split to 2 transfers:

AWADDRRW = 0x1000, WDATARW = xxxxxxxx543210xx, WSTRB = 0E

AWADDRRW = 0x1004, WDATARW = xxxxxx76xxxxxxxx, WSTRB = 10

If we use BE-8, then

AWADDRRW = 0x1000, WDATARW = xxxxxxxx325476xx, WSTRB = 0E

AWADDRRW = 0x1004, WDATARW = xxxxxx10xxxxxxxx, WSTRB = 10

When using BE-32, unaligned access is not permitted and leads to a data abort.

3.      Half-word-sized, unaligned store

Register r0 = 0x76543210,  r6=0x1000 and we execute  STR  r0, [r6, #1]

In little-endian mode:

AWADDRRW = 0x1000, WDATARW = xxxxxxxxxx3210xx, WSTRB = 06

If we use BE-8, then

AWADDRRW = 0x1000, WDATARW = xxxxxxxxxx1032xx, WSTRB = 06


When using BE-32, unaligned access is not permitted and leads to a data abort.

--

I ran a test using BIGENDINIT=1 with the following code (r6=0x1000):

                        ; literal pool loads

                        LDR    r0, =0x03020100

                        LDR    r1, =0x07060504

                        LDR    r2, =0x0B0A0908

                        LDR    r3, =0x0F0E0D0C

                        STR     r0, [r6]

                        STR     r1, [r6, #4]

                        STM    r6, {r0-r3}

Note: The STM uses an incrementing address, so r0 is stored at 0x1000, r1 at 0x1001, r2 at
0x1002, r3 at 0x1003.

On the AXI write port, I see the following transfers:

WDATARW = xxxxxxxx00010203,  WSTRB = 0F             ; first STR, AWLEN=0

WDATARW = 04050607xxxxxxxx, WBSTRB = F0           ; second STR, AWLEN=0

WDATARW = 0405060700010203, WSTRB = FF              ; STM registers r0, r1, AWLEN=1

WDATARW = 0C0D0E0F08090A0B, WSTRB = FF          ; STM registers r2, r3, AWLEN=1

The ARM registers are little endian so the data on the bus in BE-32 is swapped with respect to
the register bank.

Rate this article

[Bad]
|
|
[Good]
Disagree? Move your mouse over the bar and click

Did you find this article helpful? Yes No

How can we improve this article?

Link to this article
Copyright © 2011 ARM Limited. All rights reserved. External (Open), Non-Confidential