|ARM Technical Support Knowledge Articles|
DAPEN and DBGEN are input signals to the Cortex-M3/Cortex-M4 core level logic in a chip.
DAPEN enables debugger access to the AHB-AP and therefore to the entire Cortex-M3/Cortex-M4 memory map including debug registers (assuming that debug features have been included in the chip design).
DBGEN enables debug events such as Breakpoints which can Halt the processor or trigger a Debug Monitor exception.
By default, the Cortex-M3/Cortex-M4 core level is instantiated in a standard Integration Level of logic which provides just a single input signal DBGEN, and asserts DAPEN if DBGEN is asserted and a debugger is connected, as this is generally what is wanted. Chip designers may choose to drive these signals independently, and may tie them off or control them from other logic on the chip.
If your chip has DAPEN=1 and DBGEN=0, the debugger is able to access memory, but is not able to trigger a debug event. Note that executing a BKPT (breakpoint) instruction opcode cannot be ignored when DBGEN is de-asserted, so this case results in a Hard Fault exception. Because the FPB unit generates breakpoints by returning a BKPT opcode in place of the instruction opcode in that memory location, this Hard Fault behavior applies also to breakpoints generated by the FPB. (This behavior of FPB Breakpoints is subject to review and may potentially be modified in a future release after Cortex-M3 r2p1 and Cortex-M4 r0p1.)
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