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Although this is not an intended usage mode, it should be possible.
However, early versions of the Cortex-M3 did not buffer the data correctly. If the TPIU's Part Number (bits[3:0] of the Peripheral ID1 at 0xE0040FE4 plus bits[7:0] of the Peripheral ID0 at 0xE0040FE0) is 0x923 (ie. TPIU-M3), and the revision code (bits [7:4] of the Peripheral ID2 at 0xE0040FE8) is less than 3, it is likely that in integration mode trace data won't be buffered up correctly in the FIFOs.
For TPIU-M3 revision 3 and above and for TPIU-M4 (Part Number 0x9A1), this register is used as 3 bytes of information, with a count of valid bytes. These can then be buffered up and decoded as described in the Embedded Trace Macrocell Architecture Specification, ARM IHI 0014 revision O (letter "o") and above.
It is important to pay attention to the "valid" bits at the top of each word of trace data.
The ETM trace should stall when the TPIU FIFO is full.
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