|ARM Technical Support Knowledge Articles|
Applies to: Cortex-A5
The process for ACP access using coherent transfer is as follows: § Check if line is in cluster § Lookup ACP transaction address (AxADDRS[31:0]) in SCU tag RAMs § Read hit § Data returned to ACP port § Read miss § Transaction forwarded to AXI masters, data returned to ACP only § Write hit § Line evicted & invalidated, data merged with ACP write data § Transaction forwarded to AXI master § Write miss § Transaction forwarded to AXI masters So the ACP writes cause the cache line to be evicted from L1 (if present) and L2 updated. The DMA transfer writes to L2 so does not pollute the L1 cache.
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