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Applies to: Cortex-A5
The Cortex-A5 supports 5 outstanding data reads: 2 are due to load or PLD instructions (there are 2 data linefill buffers) and the other 3 are due to automatic data prefetch.
The prefetcher can be configured to prefetch 0 (disabled), 1, 2 or 3 cache lines ahead using cp15 auxililiary control register.
The prefetcher recognises a sequence of 3 data cache misses at a fixed stride pattern, which lies within a +/- 4 cache line window e.g.
0x0, 0x40, 0x80, then the data perfetcher will begin to fetch 0xC0, 0x100, etc.
Any intervening stores or loads which hit in the data cache do not interfere with the recognition of the cache miss pattern.
For Cortex-A5 MPCore, the automatic perfetcher is not used for memory regions marked with the shareable attribute.
For very short sequences, or for irregular pattern fetches, data prefetching can be done explicitly using the PLD instruction.
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