|ARM Technical Support Knowledge Articles|
Applies to: DMC-400 DDR3/LPDDR2 Memory Controller
DMC would perform sub-word writes to memory atomically depending on whether the ECC is configured or not.
In a DMC-400 without ECC, the sub-word write happen simply using the write strobes.
The AXI WSTRB signals determine the valid bytes to be overwritten.
These strobes are driven out the memory so only valid bytes are overwritten in the DRAM.
In a DMC-400 with ECC configured, the sub-word write requires the data to be read back in from DRAM, so the ECC code can be calculated across the whole new word.
The DMC performs Read-Modify-Write (RMW) in hardware, automatically.
The incoming write causes a read to memory, so the data can be merged together and then written back out.
Article last edited on: 2011-08-22 17:19:24
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