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If I do not need all of the CCI-400 slave interfaces or master interfaces, what can I do?

Applies to: CCI-400 Cache Coherent Interconnect

Answer

The removal of logic associated with unused interfaces is not supported directly. However, by tying off interfaces and optimizing during synthesis, much of the redundant logic will be removed. To do this, you would need to:

SIx_W_ID_WIDTH = 1
SIx_R_ID_WIDTH = 1
SIx_W_MAX = 2
SIx_R_MAX = 2
SIx_AR_HNDSHK_MODE = 2 (bypass)
SIx_R_HNDSHK_MODE = 2 (bypass)
SIx_AW_HNDSHK_MODE = 2 (bypass)
SIx_W_HNDSHK_MODE = 2 (bypass)
SIx_B_HNDSHK_MODE = 2 (bypass)
SIx_AC_HNDSHK_MODE = 2 (bypass)
SIx_CR_HNDSHK_MODE = 2 (bypass)
SIx_CD_HNDSHK_MODE = 2 (bypass)

MIx_W_MAX = 2
MIx_R_MAX = 2
MIx_AR_HNDSHK_MODE = 2 (bypass)
MIx_R_HNDSHK_MODE = 2 (bypass)
MIx_AW_HNDSHK_MODE = 2 (bypass)
MIx_W_HNDSHK_MODE = 2 (bypass)
MIx_B_HNDSHK_MODE = 2 (bypass)

You can still access the internal registers if M0 is unused, but you would need to specify M0 as a target for one of the address regions. You therefore need to be careful that transactions routed to the M0 region only go to the region described by the PERIPHBASE input. Transactions to other parts of the M0 region will try to go downstream and the CCI will deadlock if it does not receive a protocol-valid response.

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