ARM Technical Support Knowledge Articles

Can I individually reset each core in the CoreTile Express A9x4?

Applies to: V2P-CA9


The CoreTile A9x4 is a multi-core processor. Customers often wish to have individual control of each cores reset line. This Knowledge Article is intended to explain how this is achieved when using the CoreTile A9x4. The example provided in this Knowledge Article demonstrates how to reset an individual core. However, the code could be modified so that individual cores are held in a reset state. 


The CoreTile Express A9x4 implements a GPIO controller that is connected to the reset signals of each core. Its base address is memory mapped at 0x100E8000.
Further information can be found in the ARM PrimeCell General Purpose Input/Output (PL061) TRM. The GPIO data register "GPIODATA" located at 0x100E8000 is used to control the reset signals of each core.

The procedure for resetting a core(s) involves toggling the corresponding core GPIODATA bit(s). This cannot be performed by the core being reset , the following table describes each core's bit position:

0 4
1 5
2 6
3 7
The GPIO controller must be configured prior to the reset sequence. A description of how to set up the data direction and data mask of the GPIO controller can be found in the TRM listed above. An example calculation of the data mask can be found in section '2.3.3 Operation of the input/output lines'.
The example attached describes how to reset core 1. Core 1, 2 and 3 are held in "loop_hold" whilst core 0 executes the reset sequence. 
The reset procedure for other CoreTile Expresses can be found in the specific TRM. 



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