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For a level-sensitive interrupt it really doesn't matter whether the peripheral has re-asserted the interrupt or kept it asserted from the first time; in either case, this is what happens (transitions refer to Figure 3-1 in the GIC Architecture specs):
1. An interrupt is asserted - state goes from INACTIVE -> PENDING (transition A1).
2. The interrupt is handled - PENDING -> ACTIVE AND PENDING (transition D). With level interrupts, you cannot differentiate between the processor keeping the original signal asserted and a 'second' interrupt asserting it; all the GIC knows is that the signal remains asserted. So, if, when the processor reads the ICCIAR the interrupt is still active (high), which it will be, the processor will transition from PENDING to ACTIVE AND PENDING because the interrupt is still pending as it hasn't gone away yet. It is only for pulse interrupts that the state transitions from PENDING to ACTIVE because by the time the processor reads the ICCIAR, the interrupt signal has been deasserted
3a. The interrupt will transition ACTIVE AND PENDING -> ACTIVE if the interrupt is deasserted whilst the interrupt is being handled (transition B2).
b. The interrupt will transition ACTIVE AND PENDING -> PENDING (transition E2) upon completion of the interrupt handler by writing to the ICCEOIR if the interrupt remains asserted.
4. If the interrupt is PENDING and the source is removed before it is handled, then it transitions PENDING -> INACTIVE (transition B1).
5. Once the interrupt is in the ACTIVE state it will transition back to ACTIVE AND PENDING (A2) if the source is reasserted before completion of the handler, or to INACTIVE (E1) if the source is no longer asserted upon completion of the handler.
Section 3.2.3 in the GIC V1 Architecture spec explains in more detail - the section below expands on the PENDING -> ACTIVE AND PENDING transition (section 2 above):
"Transition D [PENDING -> ACTIVE AND PENDING]:
For an SGI, occurs if the associated SGI is enabled and the Distributor forwards it to the CPU interface at the same time that the processor reads the ICCIAR to acknowledge a previous instance of the SGI. Whether this transition occurs depends on the timing of the read of the ICCIAR relative to the reforwarding of the SGI.
For an SPI or PPI:
* Occurs if all the following apply:
- The interrupt is enabled.
- Software reads from the ICCIAR. This read adds the active state to the interrupt.
- For a level-sensitive interrupt, the interrupt signal remains asserted. This is usually the case, because the peripheral does not deassert the interrupt until the processor has serviced the interrupt.
* For an edge-triggered interrupt, whether this transition occurs depends on the timing of the read of the ICCIAR relative to the detection of the reassertion of the interrupt. Otherwise the read of the ICCIAR causes transition C, possibly followed by transition A2."
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