|ARM Technical Support Knowledge Articles|
Applies to: Cortex-M4
In the base ARMv7-M architecture the exception-continuable instructions are LDM, LDMDB, STM, STMDB, POP, and PUSH. If a processor implements the FP extension the exception-continuable floating-point instructions are VLDM, VSTM, VPOP, and VPUSH.
For the VSQRT and VDIV floating point operations the processor performs the FP operation in parallel to stacking the registers.
For example, if the processor was executing a VSQRT.F32 s3, s1 instruction and an interrupt is received. The core would start performing the stack operation and at the same time the FPU would continue to calculate the VSQRT operation.
If lazy stacking is disabled (enabled by default), the core would push the following registers onto the stack:
PC, xPSR, R0-R3, R12 and LR
The core can push either s0-s7 or s8-s15 first depending on the FP operation being performed.
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