|ARM Technical Support Knowledge Articles|
Applies to: Cortex-M4
Revision 'C' of the Cortex-M4 Technical Reference Manual omits to mention this characteristic which is architecturally specified to be Implementation Defined.
The lazy stacking procedure may be interrupted.
The floating point (FP) instruction which triggered the lazy stacking operation has not yet been executed at the time when lazy stacking is taking place. Therefore the PC value stacked for the interrupt will point to this FP instruction, and when the interrupt handler completes, the return will be to this instruction. Re-attempting this instruction will again trigger the lazy stacking operation.
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