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Applies to: uVision Debugger


Information in this knowledgebase article applies to:


I am debugging my C8051Fxxxx firmware in the uVision simulation. Conditional branch instructions on this device take one less clock cycle to complete when the branch is not taken (e.g. JC, JNC, CJNE, etc). The simulation does not reflect this and adds one more cycle to the cycle counter.


The simulation keeps a list of cycle times for all devices that have a non-standard 8051 instruction timing. This list can only keep one cycle count per instruction. Variable instruction timings for the same instruction cannot be handled by design. The maximum amount of cycles an instruction could take is assumed.


Since the simulation assumes the worst case scenario the accuracy is fine for normal application debugging. If for some reason your application has to create timings based on instruction timings please be aware that you will have different timings on hardware. On the Silabs C8051Fxxx series this affects the following instructions:

JC   rel
JNC  rel
JB   bit, rel
JNB  bit, rel
JBC  bit, rel
JZ   rel
JNZ  rel
CJNE A, direct, rel
CJNE A, #data , rel
CJNE Rn,  #data, rel
CJNE @Ri, #data, rel
DJNZ Rn, rel
DJNZ direct, rel

Your application should not rely on cycle timings. This is not considered to be a "best practice" for timing generation.


This behavior exists in all versions.


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Article last edited on: 2012-08-20 08:29:40

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