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What kind of unaligned AMBA access can Cortex-A7 generate ?

Applies to: Cortex-A7


Regular stores (STR) are 128-bit aligned.
Regular load instructions can be unaligned e.g. LDR  r0, [r1] where r1=0x1001.

This will generate an unaligned access with address ARADDR=0x1001 and ARSIZE=64b.

NEON load/strores (VLD/VST) will be aligned to the size of the NEON element size.
In the case VST1.8 or VLD1.8, the element size is byte so the alignment is also byte.
So this is never considered to be an unaligned access (refer to the architecture reference manual
rev C Table A3-1 to see the aligment checks. Although it generates an unaligend AMBA access
considering AxSIZE, AxADDR.For example:

VST1.8   {d0,d1},[r0]            ; r0=0xF8000003
AWADDR=0xF8000003, AWSIZE=3, AWLEN=0, WSTRB=00F8
AWADDR=0xF8000008, AWSIZE=2, AWLEN=0, WSTRB=0700
AWADDR=0xF8000010, AWSIZE=2, AWLEN=0, WSTRB=0007

Note that you should design according to the AMBA spec which allows unaligned access and not to a subset of the spec supported by the processor, which might change from one processor revision to the next.

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