|ARM Technical Support Knowledge Articles|
Applies to: Versatile Express Logic Tiles
Customers who wish to implement a custom logic design in a LogicTile Express often want to interface interrupts to the CoreTile Express. This Knowledge Article describes how interrupts are routed from the LogicTile Express to the CoreTile Express.
The LogicTile Express 13MG can generate up to 4 custom interrupts, these interrupt signals are routed through the Motherboard Express IOFPGA to an attached CoreTile Express located on tile site 1.
The SB2_INT[3:0] signals are output from FPGA 1 (XC6VLX550T) of the LogicTile Express 13MG. The v2f_550t.ucf file describes the pin allocations. This file is provided as part of Application Note 233, which is supplied with the Versatile Express DVD. This can be found at the following default installation path:
NOTE: "_x_x" is the version of the Versatile Express DVD installed.
The following table summarizes the four interrupt signals and the corresponding FPGA pin allocation of the XC6VLX550T FPGA.
|Signal Name||Pin Allocation|
These signals are passed from the LogicTile Express 13MG to the Motherboard IOFPGA through the LogicTiles HDRYL lower header connectors. The connectivity_spreadsheet.xls spreadsheet describes the connector mappings. This can be found at the following default installation path:
The following table outlines which connector pin each interrupt is allocated.
|Signal Name||Connector Pin|
The Motherboard IOFPGA then routes the SB2_INT[3:0] signals to the attached CoreTile Express on tile site 1. They are passed to the CoreTile Express as IRQs on the SB_IRQ bus. These IRQ signals are fed into the attached CoreTile's interrupt controller. The IRQ signals are passed to the Shared Peripheral Interface (SPI) lines of the interrupt controller and are identified by a specific ID number. The following table describe the CoreTile Express relative mappings:
|Signal Name||IRQ Number||ID Number|
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