|ARM Technical Support Knowledge Articles|
Applies to: PL08x DMAC (DM & SM)
If a low priority channel (channel 6 or 7) is granted, the maximum wait for a higher priority channel to be granted is one quad-word, i.e. the depth of the FIFO. This is a special feature of channels 6 and 7 to avoid saturation of the bus.
If one of the higher priority channels is currently granted (channels 0 - 5), then the current DMA burst (not AHB burst), which could be up to 1KB, will complete BEFORE re-arbitration. When re-arbitration takes place, the highest priority requesting channel will be granted.
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