|ARM Technical Support Knowledge Articles|
Some customers designing their own custom IP on the LogicTile Express board may want to access any type of RAM available on the CoreTile Express board. This is possible providing a slave port is present on the CoreTile Express. This is the case with the CoreTile Express A9x4.
The ARM CoreTile Express boards contain some sort of RAM, that can be DDR SDRAM and/or AXI/System RAM for example. For accurate information about the memory present on the CoreTile Express A9x4, please see the relevant Technical Reference Manual. This is available from the Versatile Express DVD that ships with the board as well as from the ARM Infocenter.
However, some pre-configuration of the TrustZone Protection Controller present on board will be needed for non-secure accesses. This Knowledge Article addresses this common question in custom logic designs.
The memory interface to DDR on the CoreTile Express A9x4 board utilizes a PL341 Dynamic Memory Controller which is already initialized by the on board ARM Boot Monitor. Please refer to the
sys_dmc_v2p_ca9.s file available from the Versatile Express DVD at the following default installation path:
C:\Program Files (x86)\Versatile_Express_3_0\software\Boot_Monitor\Platform\Source
This assumes a Motherboard Express board is also being used. The PL341 DMC should not need any further configuration.
However, some peripherals on the CoreTile Express are protected by the BP147 TZPC (TrustZone Protection Controller), including for example the PL341 and AXI RAM present on the CoreTile Express A9x4 board. From reset, the TZPC marks some areas of the memory map as Secure Access only. In order to access these peripherals, the default configuration need to be changed to perform non-secure transactions. A DECERR response will occur if this is not correctly configured.
The TZPC is memory mapped, please refer to the CoreTile Express memory map available from the board TRM. The set of programmable registers is described in the TZPC reference manual available from the Versatile Express DVD and the ARM Website.
For example, on the CoreTile Express A9x4 board, the TZPC is located at
0x100E6000. The TZPC signals are described on Table 3-12 "TZPC signals" of the CoreTile Express A9x4 TRM. On this table the AXI RAM is protected by the TZPCDECPROT1 signal which is secure by default, therefore to configure non-secure accesses to the AXI RAM, bit 5 of the TZPCDECPROT1Set register (see offset from base address on the TZPC TRM) must be set to 1. The TZPCDECPROT1 signal "Cortex-A9 Coherency Port" must also be set to 1.
Beware: On the V2P-CA9 board, the entire system can be accessed via the "ACP" port, however some ACP sideband signals are tied off inside the test chip, therefore the transactions via the ACP port are not coherent.
Did you find this article helpful? Yes No
How can we improve this article?