ARM Technical Support Knowledge Articles

Can you explain the generic timer architecture on Cortex-A7 and Cortex-A15 ?

Applies to: Cortex-A7

Answer

For CA7/CA15, there has been an effort to standardize the timer on a common specification, which 
now forms part of the Architecture Reference Manual rev C (in terms of frequency, accuracy) known 
as the generic timer.

The CPUs have one generic timer block per CPU. However, the clock part of the timer is external 
to the CPU with the reference time being passed to the CPU via the 64-bit CNTVALUEB[63:0] input. 
The generic timers block contains 4 timers (a set of control registers and comparators against 
the reference time), for secure, non-secure, hypervisor and virtual timer. Each of the 4 timers 
signals an interrupt to the GIC via a private peripheral interrupt.

There is an implementation difference between A7 and A15 in the timer power domains. The timers 
block is within the Vcpu power domain in the case of Cortex-A7. The block containing all the 
timers on the A15 is in the non-CPU power domain, so can remain powered on (with the rest of the 
SCU+L2 logic) while individual CPUs are powered off, and can generate interrupts.

The system counter which generates CNTCALUEB time signal should be in an always-on clock domain, 
so that the clock is always running. It is expected to increment at a rate of between 1MHz and 
50MHz to implement a real time clock. The counter may support low power modes (switch to lower 
frequency operation – in which case the increments of the count are larger).

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