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Applies to: Cortex-A7
Refer to section 2.1.1 for DCU read allocate mode description. By default, L1RADIS=0, L2RADIS=0 and read allocate mode is enabled. The idea of read allocate mode is to prevent filling the cache with unnecessary data when initializing a large block of memory. When a complete cache line is written before the corresponding cache linefill has completed, and this happens on 3 consecutive cache lines, then the CPU switches into L1 read allocate mode. In this mode, we stop allocating data to the L1 D$ on a write, so we only allocate data on a read. There is equivalent functionality for the L2 DCU, which is entered after 127 full cache line writes. By setting L1RADIS=1 or L2RADIS=1, we disable the entry into read allocate mode, so the CPU will remain always in "write allocate", which means allocating on a read miss or on a write miss.
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