|ARM Technical Support Knowledge Articles|
The architecture defines several alternate possibilities and "Implementation Defined" cases. A pragmatic understanding of the processor's behavior may be easier to picture than the full architectural description.
The processor provides a very minimal implementation of Exclusives in order to minimize gatecount.
It ignores the shareable attribute of the memory region.
The local monitor's Exclusives Reservation Granule is 4GB, meaning that no address information is stored in the local monitor.
Any LDREX instruction will issue a bus access marked with EXREQx = 1'b1. This will leave the local monitor in Exclusive state. If the memory system includes a global exclusive monitor covering this address, the monitor should record a tag for this address from this bus master.
A STREX will only appear on the bus if the local monitor is already in the Exclusive state. The STREX will be marked with EXREQx = 1'b1 and the processor will be sensitive to EXRESPx (as the status value returned in Rd) irrespective of shareability.
Therefore the memory system must return the correct value of EXRESPx for any STREX. This will be:
-0 for any memory address which cannot be written by any other agent in the system (exclusivity guaranteed by design)
- (x <> t) for any memory which is managed by an external exclusive monitor (exclusive success if the address matches the valid current tag for this master, otherwise exclusive fail)
- 1 for any memory address which is not managed by an external exclusive monitor but can be modified by another agent in the system (exclusivity cannot be determined or depended upon)
EXREQx is an additional ("sideband") signal timed in the address phase of the AHB-Lite protocol. EXRESPx is a sideband signal timed in the corresponding data phase of AHB-Lite. This behavior may appear on the System Bus (EXREQS, EXRESPS) or D-Code Bus (EXREQD, EXRESPD).
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