ARM Technical Support Knowledge Articles

How do I reset individual CPUs on the CoreTile Express A15_A7 (TC2)?

Applies to: V2P-CA15-CA7

Answer

The V2P-CA15_CA7 (CoreTile Express A15_A7) implements an SCC (System Configuration Controller) register that has direct control of the reset lines to the V2P-CA15_CA7 test-chip (TC2).
The following bits within the 'Reset control register' CFGREG6 correspond to the V2P-CA15_CA7 processor reset lines:

CPU Bit
Cortex-A15_0 2
Cortex-A15_1 3
Cortex-A7_0 16
Cortex-A7_1 17
Cortex-A7_2 18

Further information on CFGREG6 can be found in the V2P-CA15_CA7 Technical Reference Manual. This can be found in the Versatile Express DVD and on the ARM website.

The values assigned to these bits can be:

For example, the following 'Reset control register' CFGREG6 values define:

0x5FFFFFF3           ; Reset control - (CA7s running, CA15s reset) 

The SCC 'Reset control register' CFGREG6 can be configured in two ways. Either before the main power-on-reset, or during runtime.

Power-On Reset

Prior to the main power-on-reset, the V2P-CA15_CA7 DCC (Daughterboard Configuration Controller) performs daughterboard configurations. The 'board.txt' file defines these configurations. The V2P-CA15_CA7 'board.txt' file can be found in the Versatile Express Mass Storage Device in the following directory:

F:\SITE1\HBI0249A

If the entry for the SCC 'Reset control register' CFGREG6 is not already present in the list of [SCC REGISTERS] then it will need to be added as follows.

  1. Increment the number of SCC registers by incrementing the entry:

    TOTALSCCS:   

  2. Add the SCC 'Reset control register' CFGREG6 entry:

    SCC: 0x018 <register_value>

It is required that the Boot CPU / Cluster is not held in reset.  This can be done by changing the Boot CPU / Cluster in the SCC 'System information register' CFGREG48 so that it reflects a processor not held in reset:

SCC: 0x700 0x00320003           ; CFGRW48 - [25:24] = Boot CPU, [28] = Boot Cluster

Boot CPU Bit [28] Bits[25,24]
Cortex-A15_0 0b1 0b00
Cortex-A15_1 0b1 0b01
Cortex-A7_0 0b0 0b00
Cortex-A7_1 0b0 0b01
Cortex-A7_2 0b0 0b10

Further information on CFGREG48 can be found in the V2P-CA15_CA7 Technical Reference Manual. This can be found in the Versatile Express DVD and on the ARM website.

At Runtime

During runtime software can write directly to the SCC 'System information register' CFGREG48 and 'Reset control register' CFGREG6. This can be done by writing to the memory mapped address 0x7FFF_0700 and  0x7FFF_0018 respectively.

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