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How are Memory Type and Memory Attributes represented on the AHB-Lite bus interfaces of Cortex-M3 and Cortex-M4?

Applies to: Cortex-M3, Cortex-M4

Scenario

The ARMv7-M Architecture Reference Manual (ARMv7-M ARM) defines Memory Types of Normal, Device, and Strongly Ordered, and additional attributes (where applicable) of Shareability and Cache Allocation policy.

As these processors do not contain an inner (or Level 1) cache, information about caching is used only to signal these settings to any outer level of cache which may be present in the memory system. The cache information has no meaning inside the Cortex-M3 or Cortex-M4 processor.

The Architecture defines a system address map dividing the 4GB address range into named regions aligned on half-GB boundaries, each having a default Memory Type and attributes. Table B3-1 in the ARMv7-M ARM defines these as:

  Address range          Name       Type and Attributes  
  0x00000000-0x1FFFFFFF  Code       Normal Cacheable, Write-Through, Allocate on read miss
  0x20000000-0x3FFFFFFF  SRAM       Normal Cacheable, Write-Back, Allocate on read and write miss
  0x40000000-0x5FFFFFFF  Peripheral Device, Non-shareable
  0x60000000-0x7FFFFFFF  RAM        Normal Cacheable, Write-Back, Allocate on read and write miss
  0x80000000-0x9FFFFFFF  RAM        Normal Cacheable, Write-Through, Allocate on read miss
  0xA0000000-0xBFFFFFFF  Device     Device, Shareable
  0xC0000000-0xDFFFFFFF  Device     Device, Non-shareable
  0xE0000000-0xFFFFFFFF  (System space, of which:

    0xE0000000-0xE000FFFF   Private Peripheral Bus   Strongly Ordered
    0xE0010000-0xFFFFFFFF   Vendor System            Device (Non-shareable)  
 
                         )

The default Cacheable regions above are implicitly Non-shareable.

If the processor hardware is configured to include the optional Memory Protection Unit (MPU), the Memory Type and attributes of most of these regions can be modified by programming the TEX:S:C:B fields of the MPU Region Attribute and Size Register for an MPU region covering a specified address range.

Note: The default memory regions named "Device" and "Peripheral" are non-executable. This can be overridden by the MPU. The System space is always non-executable and this cannot be overridden.

Answer

The AMBA 3 AHB-Lite bus protocol defines only two signals, HPROT[3:2], to indicate memory type and attributes. This is compatible with ARMv5 Architecture and earlier (Cacheable and Bufferable properties), but is insufficient to represent the expanded Memory Model in ARMv6 and ARMv7 architectures. For this reason, the HPROTx[3:2] signals on Cortex-M3/Cortex-M4 AHB-Lite interfaces are augmented by address phase sideband signals MEMATTRx[1:0] (where 'x' represents 'I', 'D' or 'S' for the three AHB-Lite bus interfaces on the processor).

MEMATTRx[1] indicates Shareability of the memory area addressed by a bus access. Shareable memory is considered to be accessible by agents other than the local processor, and therefore the memory system must take care to ensure that all observers of such memory will see a coherent view of the content of that memory. This is relevant to any levels of cache in the memory system. Shareable memory (if cacheable) must either not be cached, or must be cached in such a way that all observers see the same cached value. For simple, single processor systems and for systems not containing caches, Shareability has no relevance for Cortex-M3 and Cortex-M4. (Other processors may use Shareability settings to affect other aspects of their bus accesses, such as whether to signal Exclusive accesses to a Global Exclusive Monitor in the shared memory system.)

MEMATTRx[0] is combined with HPROTx[3:2] to indicate Memory Type, and if applicable, cache properties.

The mapping is described in the Cortex-M3 Integration and Implementation Manual (IIM), but is missing from some versions of Cortex-M4 IIM. The mapping is:

  MEMATTRx[0]  HPROTx[3]  HPROTx[2]   Description 
     0           0          0         Strongly Ordered 
     0           0          1         Device
     0           1          0         Normal, Non-cacheable
     0           1          1         Normal, Write-Through cacheable, allocate on read and write miss
     1           0          x         Invalid
     1           1          0         Normal, Write-Through cacheable, allocate on read miss
     1           1          1         Normal, Write-Back cacheable, allocate on read miss 

For the Code region, the Code Bus interfaces (I-Code and D-Code) have the Memory Type and Attributes tied off to represent the Code region default setting of Non-Shareable, Normal, Write-Through cacheable, allocate on read miss. (MEMATTRx[1:0]:HPROTx[3:2] = 4'b0110). These tieoff values are incorrectly reported in some editions of the Cortex-M3 and Cortex-M4 IIMs.

The Private Peripheral Bus region does not map onto any of the AHB-Lite interfaces. It is partially internal to the processor, and partly exported on the External PPB interface, which is an AMBA APB protocol interface, and hence does not support indication of Memory Types.

On the System bus interface, the Memory Type and Attributes are indicated in accordance with the preceding discussion. When the MPU is used to specify memory Type and Attributes by MPU region, the full mapping from MPU Attributes to external bus signalling is:

  TEX:S:C:B   Description                      MEMATTRS[1:0]:HPROTS[3:2]

  000 0 0 0   Strongly Ordered                     10           00
  000 0 0 1   Device, Shareable                    10           01
  000 0 1 0   WT, Non-shareable                    01           10
  000 0 1 1   WB, Non-shareable                    01           11
  000 1 0 0   Strongly Ordered                     10           00
  000 1 0 1   Device, Shareable                    10           01
  000 1 1 0   WT, Shareable                        11           10
  000 1 1 1   WB, Shareable                        11           11
  001 0 0 0   Normal Non-cacheable, Non-shareable  00           10
  001 0 0 1   Reserved                             00           01
  001 0 1 0   Implementation Defined               10           10
  001 0 1 1   WBWA, Non-shareable                  10           11
  001 1 0 0   Normal non-cacheable, Shareable      10           10
  001 1 0 1   Reserved                             10           01
  001 1 1 0   Implementation Defined               10           10
  001 1 1 1   WBWA, Shareable                      10           11
  010 0 0 0   Device, Non-shareable                00           01 *
  010 0 0 1   Reserved                             00           01
  010 0 1 0   Reserved                             00           10
  010 0 1 1   Reserved                             00           11
  010 1 0 0   Device, Non-shareable                00           01 *
  010 1 0 1   Reserved                             10           01
  010 1 1 0   Reserved                             10           10
  010 1 1 1   Reserved                             10           11
  011 0 0 0   Reserved                             00           00
  011 0 0 1   Reserved                             00           01
  011 0 1 0   Reserved                             00           10
  011 0 1 1   Reserved                             00           11
  011 1 0 0   Reserved                             10           00
  011 1 0 1   Reserved                             10           01
  011 1 1 0   Reserved                             10           10
  011 1 1 1   Reserved                             10           11
  100 0 x x   Normal Non-cacheable, Non-shareable  00           10
  100 1 x x   Normal Non-cacheable, Shareable      10           10
  101 0 x x   WBWA, Non-shareable                  00           11
  101 1 x x   WBWA, Shareable                      10           11
  110 0 x x   WT, Non-shareable                    01           10
  110 1 x x   WT, Shareable                        11           10
  111 0 x x   WB, Non-shareable                    01           11
  111 1 x x   WB, Shareable                        11           11

where

  WT = Normal Cacheable, Write-Through, allocate on read miss
  WB = Normal Cacheable, Write-Back, allocate on read miss
  WBWA = Normal Cacheable, Write-Back, allocate on read and write miss

Note: Where the caching attributes differ between "inner" (L1) and "outer" (L2), it is the outer policy which is indicated on the bus signals.

* Note also: for the "Device, Non-shareable" cases marked '*', older versions of Cortex-M3 incorrectly signalled a Strongly Ordered setting of MEMATTRS[1:0]:HPROTS[3:2] = 4'b0000.

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