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Where will an ARMv8-A processor start execution after reset?

Applies to: ARMv8 Architecture


On coming out of reset, execution will start in the highest implemented EL (EL3 on the Cortex-A5x family of processors).

Which exception state execution starts in is IMPLEMENTATION DEFINED.  On processors that support both execution states it would be common to have a signal to control the initial state (e.g. the AA64nAA32 signal on the Cortex-A57).

There is also a Reset Management Register (RMR_ELn) of the highest implemented EL, which is capable of using both AArch32 and AArch64, controls the Execution state that the processor boots into and allows request of a Warm reset.

Where initial execution starts depends on the execution state:


The start address is IMPLEMENTATION DEFINED.  As with the exception state, it is typical to control this via a signal (e.g. RVBARADDR on the Cortex-A57).  Software can read the reset address from the RVBAR_ELn register (where 'n' is the highest implemented EL).


The possible start addresses are the same as in ARMv7-A; 0x0, 0xFFFF,0000 or an IMPLEMENTATION DEFINED address. 

When an IMPLEMENTATION DEFINED address is used, a processor can report this address in the MVBAR register, or if EL3 is not implemented the RVBAR32 register.  See the Architecture Reference Manual for more details.

Article last edited on: 2015-01-09 16:41:40

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