ARM Technical Support Knowledge Articles

Can non 64B aligned WRAP4 write transfers occur on Cortex-A7 ?

Applies to: Cortex-A7


The answer is only in the case of a configuration without L2 cache integrated.

A natural eviction from L1 will use WRAP4, and will not necessarily be aligned to the start of
the cacheline.  The first quadword to be sent will match the critical quadword for the linefill, 
i.e. if the linefill fetches quadwords in the order 1, 2, 3, 0 then the eviction caused by that
linefill will send quadwords in the order 1, 2, 3, 0.

For implementations with an L2 cache, this will be hidden, as the eviction will allocate into 

In a configuration with an L2 cache, we see only INCR4 natural evictions.

We can see WRAP4 L1 evictions due to cache cleaning (clean by MVA to PoC) and all of these are 
address aligned to cache line boundaries.

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