|ARM Technical Support Knowledge Articles|
Applies to: AHB
HWDATA is guaranteed to remain at the same value when sampled at different clock edges in an extended transfer. However, it is possible that HWDATA can glitch after clock edges, returning to the same value as previously driven. It is possible to observe this behaviour when using a typical synthesis design flow, where the control signals for the HWDATA output multiplexor can change during the extended transfer, but they result in the same output value being used.
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