ARM Technical Support Knowledge Articles

Is semihosting supported in DS-5 for ARMv8?

Applies to: DS-5, DSTREAM, Fast Models


ARMv8 semihosting is supported by DS-5 v5.15 and later, for both AArch64 and AArch32, and for connections to both software models and real target hardware.

DS-5 Debugger handles semihosting by intercepting HLT 0xF000 in AArch64, or SVC instructions in AArch32 (either SVC 0x123456 in ARM state or SVC 0xAB in Thumb state).

For AArch64 code running on real target hardware, no special action needs to be taken. In this case, the target halts on the HLT instruction and the debugger handles the semihosting automatically.

When using a software model (in either AArch32 or AArch64) or for AArch32 code running on real target hardware, you must explicitly set a semihosting trap, otherwise the debugger reports:
ERROR(TAB180): The semihosting breakpoint address has not been specified

This error is reported when the debugger tries to enable semihosting, either when an image is loaded that contains the special symbols __auto_semihosting or __semihosting_library_function, or if you explicitly try to enable semihosting with set semihosting enabled on.

You can set a semihosting trap in the debugger by executing the CLI command:
set semihosting vector <trap_address>

This instructs the debugger to set a breakpoint at this address, and when this breakpoint is hit, the debugger takes control to perform the semihosting operation. How execution gets to this address from the HLT (AArch64) or SVC (AArch32) semihosting instruction depends on the program being used, the exception level (EL) that the code is executing at, how the exceptions have been set up to propagate, etc.  It is your responsibility to ensure that execution reaches this address, typically by setting the semihosting vector address to an appropriate offset in the appropriate vector table or by creating an explicit entry in the vector table that (perhaps conditionally) branches to a known offset.

In a mixed AArch64 & AArch32 system, with semihosting being used in both execution states, you must arrange for the trapping to occur at a single AArch64 trap address. The AArch64 trap address must be at an exception level that is higher than the AArch32 semihosting calling code, because exceptions can only be taken from AArch32 to a higher exception level running in AArch64. The AArch64 semihosting calling code must be at the same or lower exception level than the AArch64 trap address. For example, EL3 AArch64 startup code that switches to EL2 AArch64 then starts an AArch32 application at EL1 could all make use of a semihosting trap in EL3 AArch64.

Article last edited on: 2015-01-07 14:54:29

Rate this article

Disagree? Move your mouse over the bar and click

Did you find this article helpful? Yes No

How can we improve this article?

Link to this article
Copyright © 2011 ARM Limited. All rights reserved. External (Open), Non-Confidential