ARM Technical Support Knowledge Articles

Why is data corrupted on RD/WR transactions to DDR memory on the V2P-CA15-A7 board?

Applies to: V2P-CA15-CA7

Scenario

The maximum stable frequency for the DDR clock on the V2P-CA15_CA7 will vary between boards. A small number of V2P-CA15_CA7 boards have displayed memory corruption issues whilst accessing the DDR2 memory (0x80000000 - 0xFFFFFFFF) at the current default frequency of 400MHz. This applies to the Versatile Express DVD 5.2 and earlier.

Answer

As a workaround, customers are advised to lower the frequency of the DDR clock. The DDR clock is configured using OSC8 in the V2P-CA15_CA7 board.txt file located in the Versatile Express Mass Storage Device:

\SITE1\HBI0249A

We recommend that the DDR clock is lowered from 400MHz to 320MHz. This can be achieved by modifying the OSC8 entry to 40.0:

OSC8: 40.0                      ;DDR2 (8:1 - 320MHz)

Customers may be able to achieve higher DDR speeds and maintain system stability by testing higher values.

The default frequency of OSC8 in the V2P-CA15_CA7 board.txt file will be updated to 320MHz in the next release of the Versatile Express DVD. 

Rate this article

[Bad]
|
|
[Good]
Disagree? Move your mouse over the bar and click

Did you find this article helpful? Yes No

How can we improve this article?

Link to this article
Copyright © 2011 ARM Limited. All rights reserved. External (Open), Non-Confidential