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When is the SEVL instruction used?

Applies to: ARMv8-A

Answer

The ARM Architecture's generic event signalling mechanism (implemented via the WFE/SEV/SEVL instructions, and by architecturally implicit behaviour) is typically used when a processor is competing for a resource and finds it temporarily unavailable. The basic sequence is:
  1. Test for resource availability
  2. If unavailable, wait until release announced, then repeat
  3. If available, try to claim the resource
The "wait until release announced" code uses the event signalling mechanism as the indication a resource has been released, specifically by executing a Wait-for-Event (WFE) instruction. In A32 and earlier instruction sets, the resource contention code can make use of conditional execution to simply and efficiently decide whether a WFE was necessary or not; since conditional execution is not supported in A64, a slightly modified algorithm is required for efficient resource contention. Take, as an example, a simple spinlock (with the register initialisation code not shown):
       sev    
1:
wfe
2:
ldaxr w1, [w0]
cbnz
w1, %1b
stxr
w1, w2, [w0]
cbnz
w1, %2b
Since conditional execution is not available, failing the test for spinlock availability branches back to a WFE before reloading the lock to test it again. This obviously requires an initial SEV before entering the loop to contend for the spinlock, to guarantee the code doesn't hang waiting for an event before the first attempt to load the lock. However, in the code shown, the send event will be broadcast to all cores in the system, which is safe, but unnecessary; the purpose of the event is to break the WFE upon first entering the loop on the local processor, other cores don't need to receive any event. By providing the SEVL instruction, A64 allows local event-waits to be broken without unnecessarily waking up other cores in the system.
Note that the example algorithm shown above (except using the SEVL instruction) provides for a more elegant solution than the "traditional" spinlock used on A32 and prior instruction sets. The architectural definition of the event mechanism means that an event unrelated to the lock being contended for could already have been latched into the system; the A64 algorithm guarantees that all latched events are cleared, thereby reducing the rate of "false positives" for lock availability.

Article last edited on: 2014-12-30 21:22:35

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