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How flexible is the interrupt and excpetion priority scheme in ARMv7-M?

Applies to: Cortex-M3, Cortex-M4

Answer

ARMv7-M allows hardware implementation of between 3 and 8 bits of priority. Most exceptions (including interrupts) can be programmed to have your choice of priorities limited by the number of priority bits implemented. Priorities are encoded so that lower numbers are higher priority, so zero is a high priority value.

There are two distinct components in the priority scheme:

  - "group priority", or pre-empting priority

  - "sub-priority", or non-pre-empting priority

Group priority allows one exception to pre-empt (interrupt) the running instruction stream if the exception has strictly higher group priority than the currently executing context.

Sub-priority has no effect on pre-emption. When more than one exception with the same group priority level is pending (waiting to be serviced), sub-priority allows you to control the order in which those pending exceptions are handled.

The number of priority bits physically implemented in the hardware ('p') is selected by the chip designer at the RTL configuration stage.

The number of group priority bits 'g' can be between 0 and 7, limited by the number of physically implemented bits.

The number of sub-priority bits 's' can be between 0 and 8, limited by the number of physically implemented bits and the number of group priority bits, such thatp = g + s

The allocation of how many bits are 'g' and how many are 's' is a single global setting and is software controllable by writing to the AIRCR.PRIGROUP field.

The priority values are always considered to be 8 bits wide, with unimplemented bits appearing as zeros at the least significant positions.

For example, if the physical implementation has four bits of priority, the priority fields could be configured in software to assign the following arrangements of group- and sub-priority bits:

  gggg  0000
  ggg s 0000
  gg ss 0000
  g sss 0000
   ssss 0000

Remember to program the priorities as 8-bit data values even if not all bits are implemented; in the example above, a medium priority might be programmed as 0x70, not 0x7. The number of physically implemented priority bits in a chip can be discovered by writing 0xFF to the priority field of any exception or interrupt (preferably one which is not currently enabled) and reading the value back to see how many bits are set.

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