|ARM Technical Support Knowledge Articles|
On V7-A cores that support the Large Physical Address Extension (LPAE), the physical address space width is expanded from 32-bits (4GB) to 40-bits (1TB). However, the ARM core can still only generate 32-bit virtual addresses. When the MMU is enabled, the LPAE extensions provide access to all 40-bits of physical address space via address translation. DS-5 memory accesses (such as setting breakpoints and updating Memory/Expressions panes) are made through the core using virtual addresses, and thus have access to the complete 40-bit physical address space.
However, at times the MMU may be off or you want to bypass the MMU and access physical memory directly. In these instances you can still access the complete 40-bit physical space using an optional feature of the CoreSight DAP called the AXI-AP. If your target features an AXI-AP, you can then access 40-bit memory directly by preceding the address with the "AXI:" prefix. For instance, for the Memory view to show the contents of 0x10_A0000000 you would enter "AXI:0x10A0000000". If you wanted to examine this location using the DS-5 command line, you would use "x AXI:0x10A0000000".
If you are using the CSAT utility shipped with DS-5, you can also utilize the AXI-AP with CSAT to access the full 40-bit address space. For instance, if the AXI-AP is at index 0, then the following command sequence generates a read of one word from location 0x10_A0000000 over the AXI-AP:
drw ap0.2 0x10 # set upper byte of 40-bit address in AP register 2
dmr 0 0xA0000000 1 # specify lower word of address in the dmr command
1. The only way to specify a 40-bit physical address in DS-5 is with the "AXI:" address prefix.
2. In DS-5 for v8, 48-bit physical addressing is natively supported for all addresses.
3. If your design features an AXI-AP but you receive an error when trying to use it, you may need a modification made to your DS-5 board files. Please email firstname.lastname@example.org.
Article last edited on: 2014-02-07 21:12:05
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