|ARM Technical Support Knowledge Articles|
The vector table base addresses stored in MVBAR and the secure copy of VBAR exist in the same virtual address space. The monitor mode's vector table, MVBAR, is used for exceptions that are specifically targeted to monitor mode. This always includes SMC exceptions and externally generated aborts and interrupts when so configured using the Secure Configuration Register (SCR.) Other exception types will be handled using a vector offset from the secure copy of VBAR.
There are a number of instructions that generate software exceptions, this is their behaviour when executed in monitor mode. Note that as there is no secure Hyp mode the HVC instruction becomes undefined when executed in the secure world.
Other synchronous exception when generated in monitor mode.
|Undefined Instruction||Secure VBAR*||0x04|
|Synchronous data abort||Secure VBAR*||0x10|
|Synchronous prefetch abort||Secure VBAR*||0x0C|
Externally generated exceptions can be configured to use MVBAR or VBAR as a vector base using the Secure Configuration Register. If they are not configured to be handled using MVBAR they will use the secure copy of VBAR, even if they occur when the current processor mode is monitor.
|Asynchronous data abort||0||Secure VBAR*||0x10|
|Asynchronous data abort||1||MVBAR||0x10|
|Asynchronous prefetch abort||0||Secure VBAR*||0x0C|
|Asynchronous prefetch abort||1||MVBAR||0x0C|
Remember; due to the asynchronous nature of these aborts the cause of the exception may not have any relation to the currently executing code.
*Note forces SCR.NS=0
Article last edited on: 2014-02-17 16:25:52
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