|ARM Technical Support Knowledge Articles|
The dedicated Trace Port Interface Unit (TPIU) for Cortex-M3 and Cortex-M4 supports a synchronous parallel trace port with up to 4 bits of parallel trace data plus an output trace clock, and a UART-style single wire output, often multiplexed with another pin function.
Chip designers may choose to implement, neither, either, or both of these options for trace output from their chip.
Internally, the processor may implement some or all of the following trace sources:
ETM - instruction trace ITM - "printf-style" instrumentation trace explicit in program code DWT - data trace
The current output method for the TPIU is specified by TPIU_SPPR.TXMODE
The mutually exclusive choices are:
00 = Parallel trace port mode. 01 = Asynchronous SWO, using Manchester encoding. 10 = Asynchronous SWO, using NRZ encoding.
It is technically possible but usually not practical to direct instruction trace to the serial output.
"When one of the two SWO modes is selected, bit  of TPIU_FFCR enables the formatter to be bypassed. If the formatter is bypassed, only the ITM and DWT trace source passes through." (Implication: selecting a SWO mode but not bypassing the formatter would allow all trace to be sent to SWO.)
This would only be practical in a system where the processor runs extremely slowly and the trace clock can be run several times faster than the processor, because at any normal operating frequency the processor would generate much more ETM trace than the SWO bandwidth could deal with.
Alternative trace solutions may be available on chips using generic CoreSight trace infrastructure components which have more flexibility. For example, a wider parallel trace port, and a stand-alone ITM with a private SWO output.
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