|ARM Technical Support Knowledge Articles|
In a system using a GICv1 or GICv2 interrupt controller; when the interrupt handler reads the Interrupt Acknowledge Register (GICC_IAR) the ID of the highest priority pending interrupt will always be returned. There is no guarantee that highest priority interrupt will be the interrupt that caused the exception in the processor.
It is possible that in the time between an interrupt being signalled to a processor and the exception handling code acknowledging the interrupt for another, higher priority, interrupt to to arrive into the GIC. Usually this will go unnoticed in normal execution but there are a few scenarios that can expose this behaviour which can cause confusion at first glance.
Consider this scenario:
The highest priority pending interrupt is now the group 0 FIQ and this ID will be returned to the IRQ handler even though the IRQ exception was caused by a different interrupt source.
Article last edited on: 2014-07-30 15:15:13
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