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PMU counters are reading zeroes in Streamline

Applies to: ARMv7 Architecture, ARMv8 Architecture, DS-5

Scenario

Answer

  1. One of the reasons why you are seeing PMU counters reading zeroes is because the perf interface is not being correctly implemented or initialized.

    Please check the Linux Kernel perf implementation. The following files in the Linux kernel define, initialize and implement the perf interface to the PMU counters:

    • Common:
    •         ./include/linux/perf_event.h
              ./arch/arm/include/asm/perf_event.h
    • For ARMv7-A:
    •         ./arch/arm/kernel/perf_event_v7.c
              ./arch/arm/kernel/perf_event.c
              ./arch/arm/kernel/perf_event_cpu.c
              ./arch/arm/kernel/perf_regs.c
    • For ARMv8-A:
    •         ./arch/arm64/kernel/perf_event.c
              ./arch/arm64/kernel/perf_regs.c
  2. An example of these files can be seen in the Linaro git repository.

  3. Another reason why you are seeing PMU counters reading zeroes is because the permission bits have not been set. The use of these bits will depend on whether the processor implements Security Extensions. Please check the non-invasive debug configuration bits during the initialization stage in the Linux kernel:

    • PMAUTHSTATUS (Performance Monitors Authentication Status register)
      • SNI (Secure non-invasive debug features implemented)
      • SNE (Secure non-invasive debug enabled bit)
    • SDER (Secure Debug Enable register, Security Extensions)
      • SUNIDEN (Secure User Non-Invasive Debug Enable bit)
    • DBGDSCR (Debug Status and Control register)
      • DBGEN (Debug Enable bit)
  4. For further information on these bits, please refer to the following sections/chapters in the ARM Architecture Reference Manual documents (ARM ARMv7-A, ARM ARMv8-A - Registration required):

    • PMAUTHSTATUS, Performance Monitors Authentication Status register
    • DBGAUTHSTATUS, Authentication Status register
    • Non-Invasive Debug Authentication
    • Effects of non-invasive debug authentication on the Performance Monitors

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