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The ARMv7-M ARM describes address 0xE000E000 as the SCS, but the TRM and IIM describe it as the NVIC. Which is it?

Applies to: Cortex-M3, Cortex-M4


The ARMv7-M Architecture Reference Manual (ARM ARM) is the definitive reference, and describes the System Control Space (SCS) occupying a 4kB region 0xe000e000 to 0xe000efff which includes the Nested Vectored Interrupt Controller (NVIC) registers from 0xe000e100 to 0xe000ecff.

Some editions of the Technical Reference Manual (TRM) and the Integration and Implementation Manual (IIM) refer to the SCS address space loosely as being the "NVIC", for example when describing the corresponding entry in the CoreSight Debug ROM Table.

While the discrepancy is of no real significance, it would be correct to refer to the address range 0xe000e000 to 0xe000efff as being the SCS, and most of the SCS address space being occupied by the NVIC registers.

The discrepancy arises because, in the source RTL code, the entire SCS address space is decoded within the NVIC PPB interface block.

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