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What AHB-Lite burst lengths are produced by Cortex-M3 and Cortex-M4?

Applies to: Cortex-M3, Cortex-M4

Answer

Cortex-M3 and Cortex-M4 processors use AHB-Lite INCR bursts (incrementing address, unspecified number of transfers) for all data transfers (loads and stores) but not for instruction fetches. Instruction fetches use SINGLE transfers. Fixed-length burst types are not used at all.

For single load and store operations, the transfer is always marked as NONSEQ (non-sequential), meaning that each burst has a length of one transfer, and is of size = Byte, Halfword or Word, depending on data size qualifier on the instruction used.

Instructions that transfer multiple ARM registers (LDM, STM, PUSH, POP) always have a size of Word, and the burst length is equal to the number of registers in the register list transferred. Intuitively, this could be up to all 16 ARM registers R0-R15 in the programmer's register bank. However, the instruction encodings for these instructions available in the ARMv7-M instruction set allow only a maximum of 14 registers to be transferred in any one instruction.

INCR bursts are also used for stacking operations during exception entry and exit. These sequences consist of a burst of two words for PC and xPSR followed by a burst of six words for R0-R3, R12 and LR. For a Cortex-M4 that includes a Floating Point Unit (FPU), exception stacking may add a burst of 17 words for floating-point registers S0-S15 and FPSCR.[1]

Because exception entry and exit with the extended floating point stack frame automatically manage S0-S15 in accordance with the Procedure Call Standard for the ARM Architecture (AAPCS), any additional requirement for managing floating point registers at exception entry and exit is likely to require pushing and popping of only up to sixteen single precision 32-bit registers S16-S31. However, it is possible to write code which uses VLDM or VSTM to transfer any number of consecutive floating point registers up to all 32 single precision 32-bit registers, resulting in an INCR burst of 32 word transfers.

Thus the maximum burst length for Cortex-M3, or for Cortex-M4 without the FPU configured and enabled, is 14.

The maximum burst length for Cortex-M4 with the FPU enabled is 32, though in many cases will not exceed 17.

[1]In some cases, where a register in S0-S7 is pending an update at exception entry, the FP registers may be stacked using three bursts of 8, 8 and 1 transfers respectively.

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