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Can Cortex-M3 / Cortex-M4 make a simultaneous instruction fetch and data access to Code space?

Applies to: Cortex-M3, Cortex-M4

Scenario

Code space is defined in the ARMv7-M Architecture as the address range from 0x0 to 0x1fffffff. In Cortex-M3 and Cortex-M4, Code space is accessed through physically separate interfaces than the remaining addresses above 0x20000000.

Answer

The licensee of the processor configures this feature in hardware during the design of his chip, so the answer to this question is specific to each individual chip design.

The configuration decision is based upon what kind of interconnect is placed between the processor's Code space bus interfaces and the memories that they can access.

The processor is supplied to the licensee together with some example bus multiplexers which can be used for the Code space.

The "code mux" is a simple combinatorial multiplexer which requires that simultaneous accesses are not issued by the processor. This can be ensured by the chip designer tying the configuration signal DNOTITRANS to 1'b1.

The "flash mux" is a more sophisticated bus multiplexer which can arbitrate between simultaneous accesses, and therefore works most efficiently with DNOTITRANS tied to 1'b0.

Chip designers using the Cortex-M4 Integration Kit as an example design should note that comments in some versions of the Cortex-M4 Integration Kit suggest that the "flash mux" requires DNOTITRANS to be 1'b1. This is not correct. The default value for DNOTITRANS in the Integration kit is controlled by "`define ARM_CODEMUX", and the default value is 1'b1, but this can safely be changed to 1'b0 by commenting out that "`define" when using the "flash mux" or any other sophisticated bus matrix component capable of handling simultaneous requests.

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