ARM Technical Support Knowledge Articles

Why must the chip designer release "PORESETn" synchronously to FCLK?

Applies to: Cortex-M0


The "Cortex-M0 Integration and Implementation Manual", document number ARM DII 0238, or the "IIM" for short, is a document available to chip designers who have licensed the Cortex-M0 Verilog RTL for use in their chip design.

Some editions of IIM indicate that the power-on reset signal PORESETn must be deasserted synchronously to the processor clock signal FCLK on the chip.


This is a typographical error based on a slightly different implementation of resets on some other Cortex-M processors.

On some Cortex-M processors, PORESETn is a superset of the regular functional processor reset signal, and therefore must be released synchronously to the main processor clock.

On Cortex-M0, PORESETn resets only the debugger interface logic, and connects only to a reset synchronizer into the debug connection clock domain inside the processor. For this reason, there is no requirement for this signal to be synchronized externally. However, chip designers should note that this arrangement of reset signals means that a power-on reset requires both of these reset signals to be asserted.

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