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Unable to access TPIU registers, they appear to be stuck at zero

Applies to: Cortex-M3, Cortex-M4

Answer

The processor-specific Trace Port Interface Unit (TPIU) includes a clock gating signal to save power when no trace is enabled. When the unit is clock-gated, its registers read as zero and writes are ignored.

ARM suggests that, in simple chip designs, the clock gating signal is derived from DEMCR.TRCENA, meaning that the TPIU registers (like the ITM and DWT registers) are accessible when DEMCR.TRCENA is set. However, chip designers who have licensed either of these processors and who include the processor and the TPIU in their chip design, have freedom to change the clock gating signal. It may therefore be necessary to consult device-specific documentation to understand the device-specific requirements for accessing the TPIU registers.

Note that more complex chips, for example those incorporating multiple processors, may make use of a different, generic TPIU in place of the processor-specific TPIU. This will likely result in a device-specific memory map and device-specific requirements for accessing the TPIU registers.

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