|ARM Technical Support Knowledge Articles|
The Integration and Implementation Manual (IIM) is provided to chip designers who have licensed the processor. Among other things, it provides information about the behavior of physical signals on the chip.
Some editions of the IIM contain a confusing description of HMASTERD[1:0] -
"0b10 = Core instruction side accesses. These include vector fetches that are marked as data by HPROTD. This value cannot appear on HMASTERD"
Instruction side accesses are never described by HMASTERD or HPROTD. Vector fetches to Code space take place on the I-Code bus and are described by HPROTI, as correctly stated in the section on HPROTI.
HMASTERD should say:
"0b10 = Reserved. This value cannot appear on HMASTERD"
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