ARM Technical Support Knowledge Articles

Why should you care about the nIRQ/nFIQ and nIRQOUT/nFIQOUT signals toggling when there are GICC_IAR reads?

Applies to: GIC-400 Generic Interrupt Controller


The GIC-400 de-asserts all of its interrupt outputs when an interrupt is acknowledged. Then, it takes 8-9 clock cycles to recalculate the highest priority pending interrupt, and drives new values. 

The system and cores must be tolerant to the de-assertion, because the de-assertion must happen in some cases. For example, if a single Shared Peripheral Interrupt (SPI) targets multiple cores and is acknowledged by one of the cores, the interrupt must be de-asserted for all cores, because the interrupt no longer needs to be sent to them.

Various factors, including other processors, can affect the nIRQOUT and nFIQOUT outputs from the GIC-400 CPU interfaces. This means that a Power Controller must tolerate the GIC-400 asserting or de-asserting these signals at any point.

nIRQOUT and nFIQOUT are usually used as wakeup signals to a System Power Controller. You must be aware of this feature. nIRQOUT and nFIQOUT can be registered in the output, so that they can be kept stable for as long as the Power Controller needs those signals to be stable.

Article last edited on: 2015-06-24 15:58:58

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