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Accessing 64-bit peripherals using Cortex-M processors

Applies to: Cortex-M0, Cortex-M0Plus, Cortex-M1, Cortex-M3, Cortex-M4, Cortex-M7, DS-5


In many cases it is essential to have 64-bit peripherals.  For example, a system might require some timers that need to run for long time.  In such cases the peripheral design needs to cope with the nature of the bus. Therefore it needs to capture the information to ensure the processor obtains a consistent value. This is not a limitation of ARM systems. Many 8-bit microcontrollers use 16-bit timers and the same issue exists.

If a pointer to a 64-bit address is marked with the volatile keyword, it guarantees that the C/C++ compiler does not optimize away any code that accesses the location that the pointer points to.  However, it does not guarantee the type of instruction that a compiler uses to access the address. A compiler might generate an LDM/STM or an LDRD/STRD to access the 64-bit peripheral. The compiler might also generate two LDR/STR instructions to access the 64-bit peripheral, although this is not atomic for any Cortex-M system that uses 32-bit buses.

On Cortex-M0, Cortex-M0+ and Cortex-M1 processors LDRD/STRD instructions are unavailable, and unless interrupts are disabled, software should not access Device memory using load and store multiple instructions, because these operations may be interrupted and restarted. 

On Cortex-M3 and Cortex-M4, software can access Device memory using load and store multiple instructions, if the Interruptible-Continuable Instruction (ICI) field in the APSR is available1, because it means that the processor will not repeat the same transfer. 

However, like Cortex-M0, Cortex-M0+ and Cortex-M1, the Cortex-M3 and Cortex-M4 processors are connected to the memory system via an AHB-Lite interface.  Even if the processor is able to prevent 64-bit accesses being restarted, the bus fabric will still break up the accesses because the 32-bit AHB interface only supports atomicity for 8-bit, 16-bit, 32-bit transfers.  Therefore the system needs to provide some other scheme such as "doubleword buffering" to handle the 64-bit accesses atomically: 

On Cortex-M7, this design issue is not so complicated because AXI supports 64-bit transfers. However, if the peripheral is connected via the 32-bit peripheral AHB, it will have the same design implications as in other Cortex-M processors.

1 The ICI field is unavailable when LDM/STM:

See also:

Article last edited on: 2015-07-31 15:17:14

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