ARM Technical Support Knowledge Articles

What is CTIINTISR[1:0]?

Applies to: Cortex-M3, Cortex-M4

Scenario

This knowledge article is intended for chip designers using Cortex-M3 or Cortex-M4 processors in the CoreSight SoC-400 tool (CSSoC).

ARM Part Number TM112, CoreSight SoC LIB400-M, provides Verilog wrapper modules for Cortex-M0, Cortex-M3 and Cortex-M4, implementing the Processor Integration Layer (PIL) required by CSSoC.

The PIL modules CORTEXM3INTEGRATIONCS and CORTEXM4INTEGRATIONCS include output signals CTIINTISR[1:0], which appear not to be documented in the relevant technical documentation.

Answer

These signals can be connected to local processor interrupt input lines to provide a capability for the cross-triggering network to generate interrupts to the processor.

They are described in the Confidential document: ARM® Cortex®-M Series Processors and CoreSight™ SoC-400 Integration Manual, ARM DIT 0049. However, all version of this document up to and including r3p2 (ARM DIT 0049E) contain a typographical error where the signal name CTIINTISR is spelled incorrectly as CTINTISR.

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