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Applies to: Cortex-M0Plus
This knowledge article is specifically intended for chip designers who have licensed the Cortex-M0+ processor for inclusion in their chip design.
Chip design companies who license of the Cortex-M0+ processor IP receive the processor design files together with an example micro-controller unit (MCU) design containing an instance of the Cortex-M0+ processor, and a set of test programs which can be run on that MCU design, for example in a logic simulation. The example MCU design and set of test programs and support files is collectively called the Integration Kit (IK).
The IK MCU includes an optional instance of the CoreSight Micro Trace Buffer-Cortex-M0+ (MTB) which provides a program flow trace capability when included in a design. The MTB is a separately licensed component. The MTB serves as a standard AHB-Lite bus to SRAM interface, but additionally includes the ability to reserve a programmable region of that SRAM as a circular buffer for trace data, and to automatically collect program flow trace into that buffer.
The MTB, in principle, occupies two separate address ranges on the bus. Its control registers occupy a 4kB aligned block of addresses at one arbitrary address range, while the SRAM itself occupies a separate arbitrary address range corresponding to the size of the SRAM. In the IK MCU, the MTB is located at a hard-coded address range of 8kB, with the control registers 4kB block based at address 0xf0002000 and with 4kB of SRAM in the consecutive address range based at 0xf0003000.
The MTB SRAM can generally be used for any purpose, including for data and for executable code, but the address range chosen in the IK MCU is in a segment of the Cortex-M0+ memory map which is always non-executable.
The following steps are correct for the "r0p1-00rel0" release of Cortex-M0+ and MTB:
To configure the IK MCU with the MTB included, the user must have completed the following steps:
- download and install the Cortex-M0+ bundle, AT590-BU-50000-r0p1-00rel0
- download the MTB bundle TM932-BU-50000-r0p1-00rel0 and merge it into the Cortex-M0+ installation
- in the integration_kit subdirectory, modify the following settings:
"ARM_CM0PIK_MTB 1" in logical/tbench/verilog/cm0p_ik_defs.v
"EXPECTED_MTB 1" in validation/tests/IKConfig.h
As the IK MCU is designed with the two MTB address ranges in a contiguous block, it is easier to move the entire MTB than to split the address ranges and move only the SRAM address range. The base addresses of the two MTB regions are coded in a number of different locations within the IK, all of which need to be updated to successfully relocate the MTB. For example, to relocate the MTB to start at address 0x30002000 (which is by default an executable address range), the following changes are required:
- in logical/cm0p_ik_mcu/verilog/cm0p_ik_sys.v
- in validation/tests/IKConfig.h
- in validation/tests/Device/ARM/cm0pikmcu/Include/cm0pikmcu.h
- in validation/tests/debugdriver.c
After these modifications are complete, it should be possible to successfully run the test programs "config_check.c" and "mtb.c" by use of the standard RunIK script as described in the Cortex-M0+ Integration and Implementation Manual (IIM), to verify the correct operation of the MTB in the relocated address range.
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