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Applies to: Cortex-M0Plus
The CoreSight Micro Trace Buffer-Cortex-M0+ (MTB) provides a program flow trace capability when included in a Coretx-M0+ design. The MTB is a separately licensed component. The MTB serves as a standard AHB-Lite bus to SRAM interface, but additionally includes the ability to reserve a programmable region of that SRAM as a circular buffer for trace data, and to automatically collect program flow trace into that buffer.
The MTB occupies two separate address ranges on the bus. Its control registers occupy a 4kB aligned block of addresses at one arbitrary address range, while the SRAM itself occupies a separate arbitrary address range corresponding to the size of the SRAM.
The MTB SRAM can generally be used for any purpose, including for storing data and/or executable code, in addition to its function of providing a flexible trace buffer. In some designs, the MTB SRAM is separate from the main system RAM, and is intended to be used exclusively for the trace buffer function. Alternatively, the MTB SRAM can be implemented as the main system RAM, and possibly the only RAM in the system, in which case the MTB SRAM is used both as the trace buffer (when tracing is enabled), and as the main data memory, and potentially also for storing executable code.
When the MTB is used exclusively as a trace buffer, enabling the tracing function does not normally introduce any additional wait-states compared to normal program execution without trace.
However, if executable code is stored in the MTB SRAM, then any branch to an address located in the SRAM will provoke both a store of a trace packet describing that branch, and the instruction fetch of the branch target opcode. This will cause wait-states on the instruction fetch until the trace packet has been written (two cycles for a normal branch packet), so this will have a tangible effect upon the processor's performance.
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